1. Technical Field
The present invention relates to a shift register and, more particularly, to a shift register having low power consumption.
2. Description of the Related Art
Shift registers store a bit of data in each register and output the stored data in response to a clock signal. Shift register chains may be any length, with as many output stages or input stages as required.
FIG. 1 is a block diagram of a shift register chain 100 with 3 stages. Referring to FIG. 1, the shift register chain 100 is made up of an (n−1)-th shift register 110, an n-th shift register 111, and an (n+1)-th shift register 112, where n denotes a positive integer. The ports q, p, s, CK_T, and RST shown in FIG. 1 on the upper part of the n-th shift register 111 are connected to ports r, q, s, CK_B, and RST, respectively, on the lower part of the (n−1)-th shift register 110. Ports r, q, s, CK_B, and RST shown on the lower part of the n-th shift register 111 are connected to ports q, p, s, CK_T, and RST, respectively, on the upper part of the (n+1)-th shift register 112. The shift registers 110, 111 and 112 may be controlled so that data can be shifted in a selected direction in the shift register chain
FIG. 2 is a block diagram of a conventional shift register 200. Referring to FIG. 2, the shift register 200 includes a multiplexer (MUX) 210, a latch circuit 220, and an inverter 230. The inverter 230 buffers data received from the latch circuit 220 and transmits the buffered data to an output port O.
The MUX 210 has two signal inputs p and r, one control input s, and one output. The latch circuit 220 stores an output signal of the MUX 210 received via an input port D in response to a clock signal, received via a clock port CKN, and outputs stored data via a first output port Q. When the latch circuit 220 receives a reset signal RST via a reset port RN, the output of the latch circuit 220 is reset.
Although not shown as such in FIG. 2, the output port Q of the latch circuit 220 is connected to the q nodes shown on the upper and lower parts of the diagram of the shift register 200 and the q nodes are connected to each other.
FIG. 3 is a circuit diagram of the latch circuit 220 of FIG. 2. Referring to FIG. 3, the latch circuit 220 includes a signal generation block 221 and a data latch block 222.
The signal generation block 221 generates a clock control signal CL, which is in phase with the clock signal received via the clock port CKN, an inverted clock control signal CLB, which is 180° out of phase with the clock signal, and an inverted reset signal RNB, which is obtained by changing by 180° the phase of the reset signal RST received from an external source via the reset port RN.
The data latch block 222 includes a master stage 222-M and a slave stage 222-S. The master stage 222-M and the slave stage 222-S latch a data signal received via the input port D in response to the signals CL, CLB, RN, and RNB, which are generated by the signal generation block 221.
The data latch block 222 may be well known to one of ordinary skill in the art and, thus, a detailed description thereof has been omitted.
The latch circuit 220 of FIG. 2 generates the clock control signal CL and the inverted clock control signal CLB in the case when data having either a logic high or logic low value is received via the input port D. Although the layout of latch circuit 220 shows two CMOS inverters connected in series, current is consumed while the outputs of the inverters are changing from one logic state to another. This current consumption may cause significant power consumption depending on the number of shift registers and the frequency of a clock signal.